The present invention generally relates to frequency divider circuits. In particular, the invention relates to what are referred to as "dual module prescalers" such as are employed in frequency synthesizers in mobile telephone communication systems. Such frequency dividers exhibit division factors switchable between 1/N and 1/(N+1), where N typically is a number such as 64 or 128. These frequency dividers work with frequencies on the order of magnitude of 1 GHz and are a component part of every GSM or DECT telephone. Due to the use of battery supplies in such devices, low power consumption is of rather critical significance.
Examples of the use and structure of such prescalers are provided in the IEEE Journal of Solid-State Circuits, Vol. 29, No. 10, October 1994, pages 1206 through 1211, and as Volume 27, No. 12, December 1992, pages 1794 through 1798. The disclosures of these articles are fully incorporated herein by reference. In these disclosed devices, further asynchronous divider expansion or expander stages respectively follow a synchronous 1:4/5 divider (also referred to as a divide by 4/5 or .div.4/5).